1. Field of the Invention
The present invention relates to a semiconductor device in which a layout pattern is formed in a plurality of wiring layers, and particularly relates to a semiconductor device capable of laying out a large number of signal lines effectively, and a layout method thereof.
2. Description of Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Memory) is configured to selectively access an arbitrary memory cell for an array portion including a large number of memory cells. The arbitrary memory cell in the array portion is corresponded to a word line and a bit line which are arranged in a matrix shape and is selected based on a unique address. A large number of decoders for selecting a memory cell corresponding to a designated address are attached to the array portion. Since such decoders are arranged with a pitch corresponding to memory cells, a line group connected to the decoders needs to be densely arranged with the same pitch as the memory cells.
Generally, word lines and bit lines are arranged perpendicular to each other. Therefore, when wiring line groups between peripheral circuits and the decoders, there are sections through which a line group in a word line extending direction and a line group in a bit line extending direction are to be connected. In this case, since the line group in the word line extending direction and the line group in the bit line extending direction are formed in different wiring layers, contacts for connecting upper and lower wiring layers are required to be formed. A structure having the line groups formed in a matrix shape in the different wiring layers and the contacts connecting the upper and lower wiring layers is disclosed, for example, in Patent References 1 and 2.    Patent Reference 1: Laid-open Japanese Patent Publication No. 2006-032944    Patent Reference 2: Laid-open Japanese Patent Publication No. Hei 10-125775
FIG. 7 shows a layout example in which two line groups formed in a matrix shape in two wiring layers are connected through contacts. As shown in the bottom part of FIG. 7, for convenience, a lateral direction is defined as an X direction and a longitudinal direction is defined as a Y direction. A plurality of lines 101 extending in the Y direction arranged in parallel with a constant pitch are formed in a first wiring layer. A plurality of lines 102 extending in the X direction arranged in parallel with a constant pitch are formed in a second wiring layer over the first wiring layer. There are formed contacts 103, each one of which is formed at an intersection between each line 101 of the first wiring layer and each line 102 of the second wiring layer. Line groups capable of bi-directionally transmitting six groups of signals in X and Y directions through six contacts 103 can be formed in FIG. 7 as a whole. If layouts of the same structure are repeatedly arranged, line groups capable of transmitting a larger number of signals can be formed.
However, in the layout of FIG. 7, there is a possibility that poor connection of the contacts 103 occurs due to trouble in the intersection of each line 101 and each line 102. In this case, sine line groups having a vast number of lines are arranged in the entire array portion, there is a problem from a viewpoint of reliability that a single poor connection of the contacts 103 directly causes a defect in an entire chip. As measures against such a problem, FIG. 8 shows a layout example achieving the same function as that of FIG. 7 by using a different layout. As different from FIG. 7, there are formed two contacts 104 arranged in the Y direction at each intersection between each of a plurality of lines 101 formed in the first wiring layer and each of a plurality of lines 102 formed in the second wiring layer. Thereby, if there is a poor connection at one of the two contacts 104 at the intersection, an electrical connection between the lines 101 and 102 can be maintained when the other contact 104 is in a normal state. Thus, the layout of FIG. 8 is capable of reducing the possibility of the poor connection in comparison with the layout of FIG. 7 so as to improve reliability of the chip.
However, when employing the layout of FIG. 8, a gap between the lines 102 extending in the X direction increases corresponding to the two contacts 104 arranged in the Y direction. That is, when comparing a pitch P1 of the lines 102 in the layout of FIG. 7 and a pitch P2 of the lines 102 in the layout of FIG. 8, a relation P2>P1 is satisfied, and therefore it becomes a problem that extra space is required corresponding to an increase in pitch in case of arranging the same number of the lines 102.